The present invention relates to the structure of a thin film insulated gate type semiconductor device (thin film transistor, or TFT) formed on an insulating surface and a production method for the same. A semiconductor device according to the present invention is used for active matrices of liquid crystal displays or the like, driving circuits of image sensors or the like, SOI integrated circuits and conventional semiconductor integrated circuits (microprocessors, microcontrollers, microcomputors or semiconductor memories, etc).
In recent years, much research has been being carried out into forming an insulated gate type semiconductor device (MISFET) on an insulating substrate or on a surface separated from a semiconductor substrate by a thick insulating film (an insulating surface). In particular, a semiconductor device in which a semiconductor layer (active layer) is of a thin film form is called a thin film transistor (TFT). In such a semiconductor device, it is difficult to obtain an element having such good crystallinity as that of a single crystal semiconductor, and usually a non-single crystal semiconductor which is not single crystal but has crystallinity has been employed.
Such a non-single crystal semiconductor has inferior characteristics as compared with a single crystal semiconductor. In particular, there has been the problem that when a reverse voltage (that is, a negative voltage in case of an N channel type TFT and a positive voltage in case of a P channel type TFT) is applied to gate electrodes, a leak current between a source and a drain is increased. This problem has been fatal particularly when a TFT is used for a switching transistor of an active matrix circuit.
It has been reported that this problem can be solved by thinning a semiconductor layer (active layer) in which channels are formed in a TFT. For example, Hisao Hayashi et al report in Jpn. J. Appl. Phys. vol. 23 (1984) L819 that they studied how the characteristics of a TFT were affected when the thickness of an active layer of crystalline silicon was changed from 100 xc3x85 to 1000 xc3x85 and obtained the desirable characteristic that as the active layer gets thinner, electric field effect mobility increases, and threshold voltage and leak current decrease.
According to this report, however, the electric field effect mobility was very low, 10 cm2/Vs at maximum, and accordingly while the above TFT could be used for a switching transistor for an active matrix circuit, it was impossible to use the TFT for a circuit for driving the active matrix circuit. According to this report, a film obtained in an as-depo state was utilized for a crystalline silicon film, and it did not have preferred crystallinity.
On the other hand, a method in which crystal growth is effected by heat annealing (solid phase growth method, SPC) and a method in which crystallization is carried out through a liquid phase state or in a solid phase by irradiating with a laser or strong light equivalent to a laser (photo annealing) has been known as methods for obtaining a semiconductor film having good crystallinity from a non-single crystal semiconductor. For example, to obtain a silicon film from non-single crystal silicon by heat annealing it has been necessary to heat an amorphous silicon film at 500 to 650xc2x0 C.
However, because of influences exerted by the substrate (including a base), it has not been possible to obtain good crystallinity by these methods without using a silicon film having a thickness of at least 500 xc3x85.
The present invention has been made in view of these kinds of problem, and an object thereof is to provide a TFT with which better characteristics can be obtained using a good crystalline silicon film.
Another object is to provide a preferable constitution of a semiconductor integrated circuit produced using a TFT having such good characteristics.
The present invention is characterized in that after an amorphous semiconductor film having a thickness of 400 xc3x85 or more is crystallized by heat annealing or photo annealing or the combined use thereof, this is wholly or selectively etched to prepare a thin crystalline semiconductor film having a thickness of 300 xc3x85 or less and this is used as an active layer (a part where channel-forming regions are formed, that is, a part on which gate electrodes are formed) in a TFT.
The present invention is characterized by the thickness of an active layer, and hereinafter the thickness means the average thickness of the prescribed region unless otherwise indicated. In a polycrystalline material, irregularities are formed thereon by the presence of grain boundaries or the like and the film thickness is sometimes abnormally small or large in places for some reason. However, since such abnormal parts will not exert influences on elements and the whole circuit, they may be ignored. It is for such reasons that attention is paid to the average thickness of the specific parts in the present invention.
The present invention is characterized as well in that the crystallinity of the semiconductor film of the active layer is excellent, and it is different from a conventional TFT in that sense. However, it is very difficult to discuss objectively crystallinity. Accordingly, excellence in crystallinity of a semiconductor film will be evaluated by the electric field effect mobility of a TFT produced therewith. While the electric field effect mobility varies depending on the gate voltage and other conditions, the maximum value thereof is considered to reflect objectively the crystallinity of the active layer in the TFT, and therefore it is suited for the evaluation. In the present invention, there can be obtained a silicon film having crystallinity sufficient to obtain the characteristic of a maximum electric field effect mobility of typically 50 cm2/Vs or more, preferably 100 cm2/Vs or more, and having a thickness of 300 xc3x85 or less.
In the present invention, two methods can be employed for the etching process described above when silicon is used as a semiconductor. The first method is characterized in that a process in which a silicon film is slightly oxidized to form a silicon oxide film and this is etched is repeated as many times as necessary. This method is excellent in controllability of etching depth as compared with a method in which a silicon film is directly dissolved by etching.
Oxidation can be carried out by head oxidation, anodic oxidation or an oxidizing agent in order to carry out oxidation in the above process. Since the thickness of the silicon film oxidized is determined by temperature or voltage and time in heat oxidation or anodic oxidation, it can very uniformly be controlled even when a large substrate is processed. The case where an oxidizing agent is used is the same. When an oxidizing agent is used, solutions of nitric acid, hydrogen peroxide, perchlorate and permanganate can be used as the oxidizing agent. For example, a mixed solution of hydrogen peroxide and ammonia can carry out oxidation very stably.
After forming a thin silicon oxide film by the above method, the silicon oxide is etched, the silicon oxide film formed on the surface is etched by exposing the silicon film to an etchant which does not etch silicon (for example a solution of a hydrogen fluoride such as 1% hydrofluoric acid or the like). This results in causing the silicon film to get thin only by the oxidized part. The problem with this method is that the necessity to repeat the process means that a longer time is taken as the depth to be etched becomes greater.
The second method is a method in which etching is carried out using a solution containing a component also positively etching silicon oxide in addition to an oxidizing agent. It is different from the first method in that the process is finished in one stage, and accordingly it is excellent in terms of it suitability for mass production. Solutions prepared by adding hydrofluoric acid to an oxidizing agent such as hydrogen peroxide or nitric acid can be used as the solution. The concentration of hydrofluoric acid and the addition amount of a buffer solution (acetic acid or the like) added can be selected to adjust the etching rate. However, etching depth will vary greatly if the components and temperature of the solution and the etching time, etc are not precisely controlled. Difficulty in precisely controlling the depth is a problem.
As described above, it can be decided considering the suitability for mass production and the precise controllability or the like which of the first method and the second method is selected.
In the present invention, the operation of etching a silicon film for thinning by the process described above may be carried out on the whole substrate, but it is more effective to carry it out only on necessary parts. Since the operation described above is required for the parts where channels in a TFT are formed, the thinning described above can be carried out on the regions including the parts on which gate electrodes are formed (channel-forming regions). Reversely, since it is advantageous that a silicon film having a certain amount of thickness is present in the regions where source and drain electrodes are provided in terms of forming contact holes, the thinning described above is preferably avoided.
When a plurality of TFT""s are present, the application of the above thinning particularly in a circuit of which low leak current is required (for example, a switching transistor for an active matrix circuit) and a circuit in which a small ON-state current is acceptable provides a large effect.
The present invention is very effective when heavy metals such as nickel, palladium, platinum, cobalt and iron are incorporated in order to promote crystallization. These heavy metal elements function as catalysts in crystallization by heat annealing in an amorphous silicon film, and they are effective in terms of shortening heat annealing time and lowering heat annealing temperatures. However, remaining of these elements in the silicon exerts an adverse influence on various TFT characteristics. In particular, it is estimated that leak current is generated with these elements as trap centers, and removal of these elements has been a topic. These elements are liable to segregate at an interface between a silicon film and another film. In particular, it was not preferable that these elements existed at an interface between a silicon film and a gate insulating film.
However, since the parts where the concentrations of these elements are large are etched as well in the silicon oxide etching process if thinning of an active layer is carried out by the above process, the concentrations of these elements for promoting crystallization can be reduced.
In this, the regions of the thinned silicon active layer region c are where the concentrations of nickel and the like are high selectively etched as shown in FIG. 11, and a lot of holes a are formed (FIGS. 11(A) and (B)).
That results in an increase in the cross-sectional area b of the channel, and the actual channel width a becomes larger than the geometric channel length d. This is convenient for a TFT of which a large ON current is required (FIG. 11(B)).
The present invention is more effective in suppressing leak current if it is applied to a TFT of an offset gate structure wherein the gate electrode is not superposed on either or one of the source and the drain.
In the present invention, all or a part of the source and drain becomes resultingly very thin, and that causes resistance in the source/drain to become very high. This rarely becomes a problem in a circuit requiring the present invention (for example, a switching transistor for an active matrix circuit); however, if the resistance in the source and drain becomes a problem, it is effective and necessary to sufficiently activate N type and P type impurity elements. For this it is effective to carry out activation using a combination of photo annealing and heat annealing. For example, after carrying out activation by irradiation with laser light, activation may beneficially be further carried out by heat annealing at 500 to 650xc2x0 C.
Because the thickness of an active layer becomes very thin in the present invention, a pulse laser having a pulse width of 10 msec or less is preferable to a continuous oscillation laser.
Because a channel-forming region is formed very thinly in the present invention, a gate insulating film of 500 xc3x85 or less may be deposited by CVD such as plasma CVD, reduced pressure CVD, atmospheric pressure CVD or ECR (electronic cyclotron resonance), or sputtering. This results in improvement in the electric field effect mobility, threshold voltage and rise characteristics (subthreshold characteristic and S value).
Conventionally, a thickness of a gate insulating film of 500 xc3x85 or less has been possible in an MOS device formed on a single crystal semiconductor wafer. This is because of the following two reasons. The first is that on a single crystal wafer a level difference at a part moving from a channel forming region to field insulating matter was very gentle on a single crystal wafer owing to a so-called LOCOS technique or the like. The second is that an oxide film used as a gate insulating film was obtained by heat oxidation and had excellent covering performance. A very thin gate insulating film was possible because of these two reasons.
However, a TFT was very disadvantageous in terms of the gentle level difference mentioned in the first point above. That is, a thickness of 500 xc3x85 or more was required in an active layer. Further, it was impossible also in the second point to obtain a gate insulating film having a sufficient thickness by heat oxidation except where heat oxidation was carried out particularly by a high temperature process of 850xc2x0 C. or higher. When heat oxidation could not be employed a non-heat oxidation method such as CVD or sputtering was inevitably employed, but a problem on a covering performance of a level difference was always involved in these methods. As a result, it has been through that it is impossible to set a thickness of a gate insulating film to 500 xc3x85 or less. However, these difficulties have been solved by the present invention.
By having set a thickness of an active layer to 300 xc3x85 or less, the covering performance of the level difference has been almost no problem even if the gate insulating film is 500 xc3x85 or thinner. In particular, an effect for making it possible to thin the gate insulating film is equal to the case of forming the gate insulating film by sputtering. A silicon oxide film which is very close to a heat oxidation film is obtained by sputtering, but sputtering has rarely been employed because the film-forming speed thereof is slow as compared with that of CVD. However, since the gate insulating film can be thinner than the conventional film, it has become possible for sputtering to compete with CVD in this regard.
In the present invention, there is also an effect that irregularities formed on an initial surface of a heavily uneven silicon film can be relieved. For example, a very heavily rough surface was formed when a laser was used with the silicon film exposed, and it was an obstacle against a covering performance of a level difference in a gate insulating film. However, it can be solved by the present invention. This is done by a process for thinning a silicon film in the present invention. For example, irregularities of about 500 xc3x85 in a process in which oxidation is carried out by a mixed solution of hydrogen peroxide and ammonia and etching is carried out by hydrofluoric acid is finally reduced to such an extent as can be almost ignored. This effect of reducing irregularities varies depending on the etchant used, and the etchant can be selected according to a required level of irregularity reduction.